Fundamentals of digital logic with VHDL design / (Record no. 30118)

MARC details
000 -LEADER
fixed length control field 01203nam a22003378i 4500
001 - CONTROL NUMBER
control field 020500840
003 - CONTROL NUMBER IDENTIFIER
control field EG-ScBUE
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20230212025533.0
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 220202s2023 nyua f 001 0 eng d
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 9781260597783 (pbk.)
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 1260597784
040 ## - CATALOGING SOURCE
Original cataloging agency StDuBDS
Language of cataloging eng
Description conventions rda
Transcribing agency StDuBDS
Modifying agency EG-ScBUE
082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 621.392
Edition number 22
Item number BRO
100 10 - MAIN ENTRY--PERSONAL NAME
Personal name Brown, Stephen D.,
Relator term author.
245 10 - TITLE STATEMENT
Title Fundamentals of digital logic with VHDL design /
Statement of responsibility, etc Stephen Brown, Zvonko Vranesic, Department of Electrical and Computer Engineering, University of Toronto.
250 ## - EDITION STATEMENT
Edition statement Fourth edition.
250 ## - EDITION STATEMENT
Edition statement International student edition.
264 #1 - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT)
Place of publication, distribution, etc New York :
Name of publisher, distributor, etc McGraw Hill,
Date of publication, distribution, etc 2023.
300 ## - PHYSICAL DESCRIPTION
Extent xv, 814 pages :
Other physical details illustrations ;
Dimensions 30 cm
336 ## - CONTENT TYPE
Content type term text
Source rdacontent
Content type code txt
337 ## - MEDIA TYPE
Media type term unmediated
Source rdamedia
Media type code n
338 ## - CARRIER TYPE
Carrier type term volume
Source rdacarrier
Carrier type code nc
500 ## - GENERAL NOTE
General note Includes index.<br/>
650 #7 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Logic circuits
General subdivision Design and construction
-- Data processing.
Source of heading or term BUEsh
650 #7 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Verilog (Computer hardware description language)
Source of heading or term BUEsh
653 ## - INDEX TERM--UNCONTROLLED
Resource For college Engineering, General
Arrived date list February2023
655 ## - INDEX TERM--GENRE/FORM
Form subdivision Reading book
700 10 - ADDED ENTRY--PERSONAL NAME
Personal name Vranesic, Zvonko G.,
Relator term author.
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Source of classification or shelving scheme Dewey Decimal Classification
Koha item type Book - Borrowing
Holdings
Withdrawn status Lost status Source of classification or shelving scheme Damaged status Not for loan Collection code Home library Current library Shelving location Date acquired Source of acquisition Cost, normal purchase price Serial Enumeration / chronology Total Checkouts Full call number Barcode Date last seen Cost, replacement price Price effective from Koha item type
    Dewey Decimal Classification     Baccah Central Library Central Library First floor 12/02/2023 Purchase 1564.00 37171   621.392 BRO 000044746 12/02/2023 1955.00 12/02/2023 Book - Borrowing

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